In recent years, the storage density of semiconductor memory devices, represented by a DRAM (Dynamic Random Access Memory), has increased. It is increasingly demanded that these devices can operate at higher speeds. The increase in storage capacity has been achieved by making memory cells smaller and by increasing the chip size. However, the miniaturization of memory cells is physically limited, and the increase in chip size leads to a reduction of yield and impairs an increase of operating speed.
To solve these problems fundamentally, there has been proposed a method such that a core unit having memory cells and an interface unit having peripheral circuits to the memory cells are provided as chips that are independent of each other, and a plurality of core chips can be allocated to one interface chip (see Japanese Patent Application Laid-open No. 2004-327474). This can greatly decrease the size of each chip. In view of this, the method is expected to increase the storage density of semiconductor memory devices even more, while preserving high yield of the semiconductor memory devices.
Assume that the core-unit and the interface unit are separate chips. The core chip and the interface chip can be fabricated in a memory process and a logic process, respectively. Generally, transistors made in the logic process can operate at higher speed than the transistors made in the memory process. Hence, if the interface chip is manufactured in the logic process, it can operate faster than the conventional interface chips. As a result, the interface chip enables the semiconductor memory device incorporating it to operate at high speed. Furthermore, the operating voltage of the interface chip can be lowered by about 1V, which helps to reduce the power consumption in the semiconductor memory device.
As described in Japanese Patent Application Laid Open No. 2004-327474, the stereoscopic stacking of the plurality of semiconductor chips permits suppression of an increase in a packaging area on the printed circuit board.
FIG. 7 is a schematic cross sectional view showing a structure of a conventional stacked semiconductor device.
As shown in FIG. 7, the conventional stacked semiconductor device includes an interposer substrate 10, a plurality of (five, in one example) semiconductor-chips 21 to 25 stacked on one surface 10a of the interposer substrate 10, and external power supply terminals 30 arranged on the other surface 10b of the interposer substrate 10. The semiconductor chips 21 to 25 can include core chips or interface chips, or both of the chips. In addition to the external power supply terminals 30, the stacked semiconductor device includes an external signal terminal that sends and receives an address, data, a command or the like. This terminal is not shown the drawings.
Each of the external power supply terminals 30 is a terminal to which a higher-potential power-supply voltage (Vdd) and a lower-potential power-supply voltage (GND) are supplied. The external power supply terminal 30 is connected to the semiconductor chip 21 via a through electrode 11 formed through the interposer substrate 10, and a bump electrode 21a arranged on the semiconductor chip 21, and a through electrode 21b arranged in the semiconductor chip 21. With this arrangement, a power supply potential is applied to an internal circuit (not shown) in the semiconductor chip 21 located in the bottom layer. The power is supplied to the semiconductor chips 22 to 25 located above the semiconductor chip 21 in a cascade manner via bump electrodes 22a to 25a and through electrodes 22b to 25b arranged on and in the semiconductor chips 22 to 25.
FIG. 8 is an equivalent circuit diagram showing only a power source portion of the stacked semiconductor device shown in FIG. 7.
In FIG. 8, r represents resistance components by the through electrodes 21b to 25b, and R represents resistance components by internal circuits of the semiconductor chips 21 to 25. The stacked semiconductor device shown in FIG. 7 is a so-called face-up stacked semiconductor device, in which each layer is stacked so that the principal surface on which the internal circuit is formed faces upward. Thus, both the higher-potential power-supply voltage (Vdd) and the lower-potential power-supply voltage (GND) need to go through the five resistance components r connected in series to reach the internal circuit of the semiconductor chip 25 located in the top layer. Accordingly, this need causes a problem such that the higher the semiconductor chip, the larger the voltage drop caused by the resistance component r, and thus, the voltage applied to the internal circuit R decreases.
This effect caused by the voltage drop becomes more apparent as electric resistances of the through electrodes 21b to 25b are larger, and further, as the number of semiconductor chips to be stacked is larger. Particularly, in recent years, there have been cases where a power source voltage is required to set to 2V or less because a lower voltage is required, and the voltage drop can easily occur due to an increase in power consumption. It is thus anticipated that the effect of the through electrode on the resistance component r cannot be neglected in the future.
For example, when polycrystalline silicon having a specific resistance of 10−5Ω is used as a material for the through electrodes 21b to 25b, radiuses of the through electrodes 21b to 25b are each 10 μm, and lengths thereof are each 50 μm, a resistance per one through electrode is then about 1.6Ω. For example, even when 20 through electrodes are connected in parallel to decrease the resistance, a resistance value (=r) per one layer is about 0.08Ω. On the other hand, when the semiconductor chips 21 to 25 are core chips of a DRAM, a power source voltage is about 1.8V, and a resistance component R by the internal circuit is about 18Ω.
When a voltage drop level is calculated based on these values to evaluate the voltage applied to the internal circuits of the semiconductor chips 21 to 25, the following are obtained: a voltage applied to the internal circuit of the semiconductor chip 21 is about 1.73V (voltage drop=about 0.07V); a voltage applied to the internal circuit of the semiconductor chip 22 is about 1.67V (voltage drop=about 0.13V); a voltage applied to the internal circuit of the semiconductor chip 23 is about 1.62V (voltage drop=about 0.18V); a voltage applied to the internal circuit of the semiconductor chip 24 is about 1.59V (voltage drop=about 0.21V); and a voltage applied to the internal circuit of the semiconductor chip 25 is about 1.58V (voltage drop=about 0.22V).
Usually, the minimum operability assuring voltage of a DRAM of which a power source voltage is 1.8V is about 1.65V. This means that the semiconductor chips 23 to 25 located above fall below this level.
The stacked semiconductor device shown in FIG. 7 is a so-called face-up stacked semiconductor device. In contrary, there is a so-called face-down stacked semiconductor device in which each layer is stacked so that the principal surface faces downward. In this face-down stacked semiconductor device also, a similar problem occurs. The problem described above occurs not only to a DRAM, but also occurs to the stacked semiconductor devices as a whole.